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xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range preliminary specification supersedes data of 2000 aug 22 2000 dec 01 integrated circuits
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2 2000 dec 01 general description the xa-s3 device is a member of philips semiconductors' xa (extended architecture) family of high performance 16-bit single-chip microcontrollers. the xa-s3 device combines many powerful peripherals on one chip. with its high performance a/d converter, timers/counters, watchdog, programmable counter array (pca), i 2 c interface, dual uarts, and multiple general purpose i/o ports, it is suited for general multipurpose high performance embedded control functions. specific features of the xa-s3 ? 2.7 v to 5.5 v operation. ? 32 k bytes of on-chip eprom/rom program memory. ? 1024 bytes of on-chip data ram. ? supports off-chip addressing up to 16 megabytes (24 address lines). a clock output reference is added to simplify external bus interfacing. ? high performance 8-channel 8-bit a/d converter with automatic channel scan and repeated read functions. completes a conversion in 4.46 microseconds at 30 mhz. alternate operating mode allows 10-bit conversion results. ? three standard counter/timers with enhanced features. all timers have a toggle output capability. ? watchdog timer. ? 5-channel 16-bit programmable counter array (pca). ? i 2 c-bus serial i/o port with byte-oriented master and slave functions. ? two enhanced uarts with independent baud rates. ? seven software interrupts. ? active low reset output pin indicates all reset occurrences (external reset, watchdog reset and the reset instruction). a reset source register allows program determination of the cause of the most recent reset. ? 50 i/o pins, each with 4 programmable output configurations. ? 30 mhz operating frequency at 2.75.5 v v dd . ? power saving operating modes: idle and power-down. wake-up from power-down via an external interrupt is supported. ? 68-pin plcc and 80-pin pqfp packages. ordering information romless rom eprom temperature range ( c) and package freq. (mhz) drawing number pxas30kba pxas33kba PXAS37kba otp 0 to +70, commercial 68-pin plastic leaded chip carrier 30 sot188-3 pxas30kbbe pxas33kbbe PXAS37kbbe otp 0 to +70, commercial 80-pin plastic low profile quad flat pack 30 sot315-1 pxas30kfa pxas33kfa PXAS37kfa otp 40 c to +85 c, industrial 68-pin plastic leaded chip carrier 30 sot188-3 pxas30kfbe pxas33kfbe PXAS37kfbe otp 40 c to +85 c, industrial 80-pin plastic low profile quad flat pack 30 sot315-1
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 3 pin configurations 68-pin plcc package p1.3/a3 p5.7/ad7/sda 10 11 12 13 14 15 16 30 31 32 33 34 35 36 p4.7/a21 p3.0/rxd0 p3.1/txd0 p3.2/int0 p3.3/int1 p3.5/t1/busw p3.4/t0 37 38 28 29 17 18 19 20 p3.6/wrl p3.7/rd v ss rstout plastic leaded chip carrier su00936 21 22 23 24 25 26 v dd ea /wait/v pp p5.0/ad0 p5.1/ad1 p5.3/ad3 p5.2/ad2 39 40 41 42 43 p5.5/ad5 p5.6/ad6/scl p1.0/a0/wrh p1.5/txd1 p1.6/t2 p1.7/t2ex p6.0/a22 60 59 58 57 56 55 54 p2.1/a13d9 p2.0/a12d8 p0.7/a11d7 p0.6/a10d6 p0.5/a9d5 v dd v ss 53 52 51 50 p0.4/a8d4 p0.3/a7d3 rst p0.2/a6d2 49 48 47 46 45 44 clkout psen ale/prog p0.1/a5d1 p6.1/a23 p0.0/a4d0 44 7654321 68 67 98 66 65 64 63 62 p4.6/a20 p4.5/cex4 p4.4/cex3 p4.3/cex2 p4.2/cex1 p4.1/cex0 p4.0/eci xtal1 xtal2 p2.7/a19d15 p2.6/a18d14 p2.5/a17d13 p2.4/a16d12 p2.3/a15d11 61 27 p2.2/a14d10 v dd p5.4/ad4 p1.4/rxd1 v ss av ref av ref+ av dd av ss p1.1/a1 p1.2/a2
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 4 80-pin lqfp package p2.2/a14d10 p2.3/a15d11 p2.4/a16d12 p2.5/a17d13 p2.6/a18d14 p2.7/a19d15 xtal2 xtal1 v dd 1 2 3 4 5 6 7 23 24 25 26 27 28 29 nc p4.7/a21 p3.0/rxd0 p3.1/txd0 p3.2/int0 p3.4/t0 p3.3/int1 30 31 21 22 8 9 10 11 p3.5/t1/busw p3.6/wrl rstout p3.7/rd low profile plastic quad flat pack su00937 12 13 14 15 16 17 v ss v ss v dd v dd p5.0/ad0 ea /wait/v pp 18 19 20 p5.1/ad1 p5.2/ad2 p5.3/ad3 32 33 34 35 36 nc p5.4/ad4 p5.5/ad5 p5.6/ad6/scl p5.7/ad7/sda av ss av ss p1.0/a0/wrh p1.1/a1 p1.2/a2 p1.3/a3 p1.4/rxd1 60 59 58 57 56 55 54 nc p2.1/a13d9 p2.0/a12d8 p0.7/a11d7 p0.6/a10d6 v ss p0.5/a9d5 53 52 51 50 v ss v dd p0.4/a8d4 v dd 49 48 47 46 45 44 p0.3/a7d3 p0.2/a6d2 rst clkout ale/prog psen 43 42 41 p0.1/a5d1 p0.0/a4d0 p6.1/a23 78 77 76 75 74 73 72 71 70 80 79 69 68 67 66 65 37 38 39 40 p1.5/txd1 p1.6/t2 p1.7/t2ex p6.0/a22 64 63 62 61 av ref av ref+ av dd av dd v ss v ss v dd p4.0/eci p4.1/cex0 p4.2/cex1 p4.3/cex2 p4.4/cex3 p4.5/cex4 p4.6/a20 nc
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 5 logic symbol v dd v ss xtal1 xtal2 port4 port5 port6 port0 port2 port1 port3 sda scl a/d inputs a21 a20 cex4 cex3 cex2 cex1 cex0 eci av dd av ref+ av ref av ss clkout ale psen rstout rst ea /wait txd0 int0 int1 t0 t1/busw wrl rd rxd0 a1 a2 a3 rxd1 txd1 t2 t2ex wrh /a0 a23 a22 address and data bus su00847a
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 6 block diagram timer 0, 1 i 2 c uart 1 uart 0 xa cpu core timer 2 watchdog timer port 0 port 1 port 2 1024 bytes static ram 32k bytes rom/eprom sfr bus port 3 port 4 input port/ a/d pca program memory bus data bus port 6 port 5 su00846
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 7 pin descriptions mnemonic pin number type name and function mnemonic plcc lqfp type name and function v ss 1, 20, 55 12, 13, 53, 54, 69, 70 i ground: 0 v reference. v dd 2, 21, 54 14, 15, 51, 52, 71, 72 i power supply: this is the power supply voltage for normal, idle, and power down operation. rst 50 47 i reset: a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. rstout 19 11 o reset output: this pin outputs a low whenever the xa-s3 processor is reset for any reason. this includes an external reset via the rst pin, watchdog reset, and the reset instruction. ale/prog 47 44 i/o address latch enable/program pulse: a high output on the ale pin signals external circuitry to latch the address portion of the multiplexed address/data bus. a pulse on ale occurs only when it is needed in order to process a bus cycle. psen 48 45 o program store enable: the read strobe for external program memory. when the microcontroller accesses external program memory, psen is driven low in order to enable memory devices. psen is only active when external code accesses are performed. ea /wait/v pp 22 16 i external access/bus wait: the ea input determines whether the internal program memory of the microcontroller is used for code execution. the value on the ea pin is latched as the external reset input is released and applies during later execution. when latched as a 0, external program memory is used exclusively. when latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. after reset is released, this pin takes on the function of bus wait input. if wait is asserted high during an external bus access, that cycle will be extended until wait is released. xtal1 68 68 i crystal 1: input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. xtal2 67 67 i crystal 2: output from the oscillator amplifier. clkout 49 46 o clock output: this pin outputs a buffered version of the internal cpu clock. the clock output may be used in conjunction with the external bus to synchronize wait state generators, etc. the clock output may be disabled by software. av dd 33 28, 29 i analog power supply: positive power supply input for the a/d converter. av ss 34 30, 31 i analog ground. av ref+ 32 27 i a/d positive reference voltage: high end reference for the a/d converter. av ref 31 26 i a/d negative reference voltage: low end reference for the a/d converter. p0.0 p0.7 45, 46, 5153, 5658 42, 43, 4850, 5557 i/o port 0: port 0 is an 8-bit i/o port with a user-configurable output type. port 0 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. when the external program/data bus is used, port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 8 mnemonic name and function type pin number mnemonic name and function type lqfp plcc p1.0 p1.7 3542 3239 i/o port 1: port 1 is an 8-bit i/o port with a user-configurable output type. port 1 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 1 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 1 also provides various special functions as described below: 35 32 o a0/wrh (p1.0) address bit 0 of the external address bus when the eternal data bus is configured for an 8-bit width. when the external data bus is configured for a 16-bit width, this pin becomes the high byte write strobe. 36 33 o a1 (p1.1): address bit 1 of the external address bus. 37 34 o a2 (p1.2): address bit 2 of the external address bus. 38 35 o a3 (p1.3): address bit 3 of the external address bus. 39 36 i rxd1 (p1.4): serial port 1 receiver input. 40 37 o txd1 (p1.5): serial port 1 transmitter output. 41 38 i/o t2 (p1.6): timer/counter 2 external count input or overflow output. 42 39 o t2ex (p1.7): timer/counter 2 reload/capture/direction control. p2.0 p2.7 5966 58, 59, 6166 i/o port 2: port 2 is an 8-bit i/o port with a user-configurable output type. port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 2 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. when the external program/data bus is used in 16-bit mode, port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. when the external data/address bus is used in 8-bit mode, the number of address lines that appear on port 2 is user programmable in groups of 4 bits. p3.0 p3.7 1118 310 i/o port 3: port 3 is an 8-bit i/o port with a user-configurable output type. port 3 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 3 also provides the various special functions as described below: 11 3 i rxd0 (p3.0): receiver input for serial port 0. 12 4 o txd0 (p3.1): transmitter output for serial port 0. 13 5 i int0 (p3.2): external interrupt 0 input. 14 6 i int1 (p3.3): external interrupt 1 input. 15 7 i/o t0 (p3.4): timer/counter 0 external count input or overflow output. 16 8 i/o t1 / busw (p3.5): timer/counter 1 external count input or overflow output. the value on this pin is latched as an external chip reset is completed and defines the default external data bus width. 17 9 o wrl (p3.6): external data memory low byte write strobe. 18 10 o rd (p3.7): external data memory read strobe. p4.0 p4.7 310 7379, 2 i/o port 4: port 4 is an 8-bit i/o port with a user-configurable output type. port 4 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 4 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 4 also provides various special functions as described below: 3 73 i eci (p4.0): pca external clock input. 4 74 i/o cex0 (p4.1): capture/compare external i/o for pca module 0. 5 75 i/o cex1 (p4.2): capture/compare external i/o for pca module 1. 6 76 i/o cex2 (p4.3): capture/compare external i/o for pca module 2. 7 77 i/o cex3 (p4.4): capture/compare external i/o for pca module 3. 8 78 i/o cex4 (p4.5): capture/compare external i/o for pca module 4. 9 79 o a20 (p4.6): address bit 20 of the external address bus. 10 2 o a21 (p4.7): address bit 21 of the external address bus.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 9 mnemonic name and function type pin number mnemonic name and function type lqfp plcc p5.0 p5.7 2330 1720, 2225 i/o port 5: port 5 is an 8-bit i/o port with a user-configurable output type. port 5 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 5 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 5 also provides various special functions as described below. port 5 pins used as a/d inputs must be configured by the user to the high impedance mode. 23 17 i ad0 (p5.0): a/d channel 0 input. 24 18 i ad1 (p5.1): a/d channel 1 input. 25 19 i ad2 (p5.2): a/d channel 2 input. 26 20 i ad3 (p5.3): a/d channel 3 input. 27 22 i ad4 (p5.4): a/d channel 4 input. 28 23 i ad5 (p5.5): a/d channel 5 input. 29 24 i/o ad6/scl (p5.6): a/d channel 6 input. i 2 c serial clock input/output. 30 25 i/o ad7/sda (p5.7): a/d channel 7 input. i 2 c serial data input/output. p6.0 p6.7 43, 44 40, 41 i/o port 6: port 6 is a 2-bit i/o port with a user-configurable output type. port 6 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 6 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 6 also provides special functions as described below: 43 40 o a22 (p6.0): address bit 22 of the external address bus. 44 41 o a23 (p6.1): address bit 23 of the external address bus. table 1. special function registers sfr bit functions and addresses reset name description address msb lsb value 3f7 3f6 3f5 3f4 3f3 3f2 3f1 3f0 adcon#* a/d control register 43e adres admod adsst adint 00h 3ff 3fe 3fd 3fc 3fb 3fa 3f9 3f8 adcs#* a/d channel select register 43f adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 00h adcfg# a/d timing configuration 4b9 a/d timing configuration 0fh adrsh0# a/d high byte result, channel 0 4b0 xx adrsh1# a/d high byte result, channel 1 4b1 xx adrsh2# a/d high byte result, channel 2 4b2 xx adrsh3# a/d high byte result, channel 3 4b3 xx adrsh4# a/d high byte result, channel 4 4b4 xx adrsh5# a/d high byte result, channel 5 4b5 xx adrsh6# a/d high byte result, channel 6 4b6 xx adrsh7# a/d high byte result, channel 7 4b7 xx adrsl# two lsbs of 10-bit a/d result 4b8 xx bcr# bus configuration register 46a clkd waitd busd bc2 bc1 bc0 note 1 btrh bus timing register high byte 469 dw1 dw0 dwa1 dwa0 dr1 dr0 dra1 dra0 ffh btrl bus timing register low byte 468 wm1 wm0 alew cr1 cr0 cra1 cra0 efh 2d7 2d6 2d5 2d4 2d3 2d2 2d1 2d0 ccon#* pca counter control 41a cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00h cmod# pca mode control 490 cidl wdte cps1 cps0 ecf 00h ch# pca counter high byte 48b 00h cl# pca counter low byte 48a 00h ccapm0# pca module 0 mode 491 ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 00h ccapm1# pca module 1 mode 492 ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 00h
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 10 reset bit functions and addresses sfr name value lsb msb address description ccapm2# pca module 2 mode 493 ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2 00h ccapm3# pca module 3 mode 494 ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 00h ccapm4# pca module 4 mode 495 ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 00h ccap0h# pca module 0 capture high byte 497 xx ccap1h# pca module 1 capture high byte 499 xx ccap2h# pca module 2 capture high byte 49b xx ccap3h# pca module 3 capture high byte 49d xx ccap4h# pca module 4 capture high byte 49f xx ccap0l# pca module 0 capture low byte 496 xx ccap1l# pca module 1 capture low byte 498 xx ccap2l# pca module 2 capture low byte 49a xx ccap3l# pca module 3 capture low byte 49c xx ccap4l# pca module 4 capture low byte 49e xx cs code segment 443 00h ds data segment 441 00h es extra segment 442 00h 367 366 365 364 363 362 361 360 i2con#* i 2 c control register 42c cr2 ena sta sto si aa cr1 cr0 00h i2stat# i 2 c status register 46c i 2 c status code/vector 0 0 0 f8h i2dat# i 2 c data register 46d xx i2addr# i 2 c address register 46e i 2 c slave address gc 00h 33f 33e 33d 33c 33b 33a 339 338 ieh* interrupt enable high byte 427 eti1 eri1 eti0 eri0 00h 337 336 335 334 333 332 331 330 iel#* interrupt enable low byte 426 ea ead epc et2 et1 ex1 et0 ex0 00h 377 376 375 374 373 372 371 370 ielb#* interrupt enable b low byte 42e ei2 ec4 ec3 ec2 ec1 ec0 00h ipa0 interrupt priority a0 4a0 pt0 px0 00h ipa1 interrupt priority a1 4a1 pt1 px1 00h ipa2# interrupt priority a2 4a2 ppc pt2 00h ipa3# interrupt priority a3 4a3 pad 00h ipa4 interrupt priority a4 4a4 pti0 pri0 00h ipa5 interrupt priority a5 4a5 pti1 pri1 00h ipb0# interrupt priority b0 4a8 pc1 pc0 00h ipb1# interrupt priority b1 4a9 pc3 pc2 00h ipb2# interrupt priority b2 4aa pi2 pc4 00h 387 386 385 384 383 382 381 380 p0* port 0 430 a11d7 a10d6 a9d5 a8d4 a7d3 a6d2 a5d1 a4d0 ffh 38f 38e 38d 38c 38b 38a 389 388 p1* port 1 431 t2ex t2 txd1 rxd1 a3 a2 a1 a0/wrh ffh 397 396 395 394 393 392 391 390 p2* port 2 432 a19d15 a18d14 a17d13 a16d12 a15d11 a14d10 a13d9 a12d8 ffh 39f 39e 39d 39c 39b 39a 399 398 p3* port 3 433 rd wrl t1 t0 int1 int0 txd0 rxd0 ffh 3a7 3a6 3a5 3a4 3a3 3a2 3a1 3a0 p4#* port 4 434 a21 a20 cex4 cex3 cex2 cex1 cex0 eci ffh
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 11 reset bit functions and addresses sfr name value lsb msb address description 3af 3ae 3ad 3ac 3ab 3aa 3a9 3a8 p5#* port 5 435 ad7/sda ad6/scl ad5 ad4 ad3 ad2 ad1 ad0 ffh 3b1 3b0 p6#* port 6 436 a23 a22 ffh p0cfga port 0 configuration a 470 note 5 p1cfga port 1 configuration a 471 note 5 p2cfga port 2 configuration a 472 note 5 p3cfga port 3 configuration a 473 note 5 p4cfga# port 4 configuration a 474 note 5 p5cfga# port 5 configuration a 475 note 5 p6cfga# port 6 configuration a 476 note 5 p0cfgb port 0 configuration b 4f0 note 5 p1cfgb port 1 configuration b 4f1 note 5 p2cfgb port 2 configuration b 4f2 note 5 p3cfgb port 3 configuration b 4f3 note 5 p4cfgb# port 4 configuration b 4f4 note 5 p5cfgb# port 5 configuration b 4f5 note 5 p6cfgb# port 6 configuration b 4f6 note 5 227 226 225 224 223 222 221 220 pcon* power control register 404 pd idl 00h 20f 20e 20d 20c 20b 20a 209 208 pswh* program status word (high byte) 401 sm tm rs1 rs0 im3 im2 im1 im0 note 2 207 206 205 204 203 202 201 200 pswl* program status word (low byte) 400 c ac v n z note 2 217 216 215 214 213 212 211 210 psw51* 80c51 compatible psw 402 c ac f0 rs1 rs0 v f1 p note 3 rstsrc# reset source register 463 r_wd r_cmd r_ext note 7 rth0 timer 0 reload register, high byte 455 00h rth1 timer 1 reload register, high byte 457 00h rtl0 timer 0 reload register, low byte 454 00h rtl1 timer 1 reload register, low byte 456 00h 307 306 305 304 303 302 301 300 s0con* serial port 0 control register 420 sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00h 30f 30e 30d 30c 30b 30a 309 308 s0stat#* serial port 0 extended status 421 err0 fe0 br0 oe0 stint0 00h s0buf serial port 0 data buffer register 460 xx s0addr serial port 0 address register 461 00h s0aden serial port 0 address enable 462 00h 327 326 325 324 323 322 321 320 s1con* serial port 1 control register 424 sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00h 32f 32e 32d 32c 32b 32a 329 328 s1stat#* serial port 1 extended status 425 err1 fe1 br1 oe1 stint1 00h s1buf serial port 1 data buffer register 464 xx s1addr serial port 1 address register 465 00h
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 12 reset bit functions and addresses sfr name value lsb msb address description s1aden serial port 1 address enable 466 00h scr system configuration register 440 pt1 pt0 cm pz 00h 21f 21e 21d 21c 21b 21a 219 218 ssel* segment selection register 403 eswen r6seg r5seg r4seg r3seg r2seg r1seg r0seg 00h swe software interrupt enable 47a swe7 swe6 swe5 swe4 swe3 swe2 swe1 00h 357 356 355 354 353 352 351 350 swr* software interrupt request 42a swr7 swr6 swr5 swr4 swr3 swr2 swr1 00h 2c7 2c6 2c5 2c4 2c3 2c2 2c1 2c0 t2con* timer 2 control register 418 tf2 exf2 rclk0 tclk0 exen2 tr2 c/t2 cp/rl2 00h 2cf 2ce 2cd 2cc 2cb 2ca 2c9 2c8 t2mod* timer 2 mode control 419 rclk1 tclk1 t2oe dcen 00h th2 timer 2 high byte 459 00h tl2 timer 2 low byte 458 00h t2caph timer 2 capture, high byte 45b 00h t2capl timer 2 capture, low byte 45a 00h 287 286 285 284 283 282 281 280 tcon* timer 0 and 1 control register 410 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 high byte 451 00h th1 timer 1 high byte 453 00h tl0 timer 0 low byte 450 00h tl1 timer 1 low byte 452 00h tmod timer 0 and 1 mode control 45c gate c/t m1 m0 gate c/t m1 m0 00h 28f 28e 28d 28c 28b 28a 289 288 tstat* timer 0 and 1 extended status 411 t1oe t0oe 00h 2ff 2fe 2fd 2fc 2fb 2fa 2f9 2f8 wdcon* watchdog control register 41f pew2 pre1 pre0 wdrun wdtof note 6 wdl watchdog timer reload 45f 00h wfeed1 watchdog feed 1 45d xx wfeed2 watchdog feed 2 45e xx notes: * sfrs are bit addressable. # sfrs are modified from or added to xa-g3 sfrs. 1. at reset, the bcr is loaded with the binary value 00000a11, where aa' is the value on the busw pin. this defaults the address bus size to 24 bits. 2. sfr is loaded from the reset vector. 3. all bits except f1, f0, and p are loaded from the reset vector. those bits are all 0. 4. unimplemented bits in sfrs are x (unknown) at all times. ones should not be written to these bits since they may be used for other purposes in future xa derivatives. the reset value shown for these bits is 0. 5. port configurations default to quasi-bidirectional when the xa begins execution from internal code memory after reset, based on the condition found on the ea pin. thus, all pncfga registers will contain ff, and pncfgb register will contain 00 when the xa begins execution using internal code memory. when the xa begins execution using external code memory, the default configuration for pi ns that are associated with the external bus will be push-pull. the pncfga and pncfgb register contents will reflect this difference. 6. the wdcon reset value is e6 for a watchdog reset, e4 for all other reset causes. 7. the rstsrc register reflects the cause of the last xa-s3 reset. one bit will be set to 1, the others will be cleared to 0. 8. the xa guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. this prevents loss of an interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write porti ons of an instruction that performs a read-modify-write operation. examples of such instructions are: and s0con,#$fb clr tr0 setb ti_0 xa-s3 sfr bits that are guarded in this manner are: adint (in adcon); cf, ccf4, ccf3, ccf2, ccf1, and ccf0 (in ccon); si (in i2con); ti_0 and ri_0 (in s0con); ti_1 and ri_1 (in s1con); fe0, br0, and oe0 (in s0stat); fe1, br1, and oe1 (in s1stat); tf2 ( in t2con); tf1, tf0, ie1, and ie0 (in tcon); and wdtof (in wdcon). 9. the xa-s3 implements an 8-bit sfr bus, as stated in chapter 8 of the xa user guide . all sfr accesses must be 8-bit operations. attempts to write 16 bits to an sfr will actually write only the lower 8 bits. sixteen bit sfr reads will return undefined data in the u pper byte.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 13 su01219 fffffh 8000h 7fffh 0000h up to 16 mb total code memory 32 kb on-chip code memory figure 1. xa-s3 program memory map su01220 ffffh 0400h 03ffh 0000h data memory (indirectly addressed, off-chip) data memory (directly or indirectly addressable, on-chip data segment 0 (bit-addressable data area) data memory (directly or indirectly addressable, on-chip 0040h 003fh 0020h 001fh 0000h data memory (indirectly addressed, off-chip) data memory (directly or indirectly addressable, on-chip other data segments (bit-addressable data area) data memory (directly or indirectly addressable, off-chip 1 kb on-chip data memory (ram) directly addressed data (1 k per segment) ffffh 0400h 03ffh 0040h 003fh 0020h 001fh figure 2. xa-s3 data memory map
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 14 functional description details of xa-s3 functions will be described in the following sections. analog to digital converter the xa-s3 has an 8-channel, 8-bit a/d converter with 8 sets of result registers, single scan and multiple scan operating modes. the a/d also has a 10-bit conversion mode that provides greater result resolution. the a/d input range is limited to 0 to av dd (3.3 v max.). the a/d inputs are on port 5. analog power and ground as well as av ref+ and av ref must be supplied in order for the a/d converter to be used. prior to enabling the a/d converter or driving analog signals into the a/d inputs, the port configurations for the pins being used as a/d inputs must be set to the aoffo (high impedance, input only) mode. a/d timing can be adapted to the application clock frequency in order to provide the fastest possible conversion. a/d converter operation is controlled through the adcon (a/d control) register, see figure 1. bits in adcon start and stop the a/d, flag conversion completion, and select the converter operating modes. when 10-bit resolution is needed, the a/d mode may be set to give 10 result bits by setting the adres bit to 1. in this mode, the a/d takes longer to complete a conversion, and the timing must be set differently in adcfg. a/d conversion modes the a/d converter supports a single scan mode and a continuous scan mode. in either mode, one or more a/d channels may be converted. the adcs register determines which channels are converted. if the corresponding bit in the adcs register is set, that channel is selected for conversions, otherwise that channel is skipped. the adcs register is detailed in figure 2. for any a/d conversion, the results are stored in adrshn, corresponding to the a/d channel just converted. for a 10-bit conversion, the two least significant bits are read from the upper end of register adrsl. these bits must be read before another conversion is begun. a/d conversions are begun by setting the a/d start and status bit in adcon. in the single scan mode, all of the channels selected by bits in the adcs register will be converted once. the adint flag is set when the last channel is converted. in the continuous scan mode, the a/d converter continuously converts all a/d channels selected by bits in the adcs register. the adint flag is set when all channels have been converted once. the a/d converter can generate an interrupt when the adint flag is set. this will occur if the a/d interrupt is enabled (via the ead bit in iel), the interrupt system is enabled (via the ea bit in iel), and the a/d interrupt priority (specified in ipa3 bits 3 to 0) is higher than the currently running code (psw bits im3 through im0) and any other pending interrupt. adint must be cleared by software. a/d timing configuration the a/d sampling and conversion timing may be optimized for the particular oscillator frequency and input drive characteristics of the application. because a/d operation is mostly dependent on real-time effects (charging time of sampling capacitors, settling time of the comparator, etc.), a/d conversion times are not necessarily much longer at slower clock frequencies. the a/d timing is controlled by the adcfg register, as shown in figure 3, table 2 and table 3. the primary effect of adcfg settings is to adjust the a/d sample and hold time to be relatively constant over various clock frequencies. two settings (value 6 and b) are provided to allow fast conversions with a lower external source driving the a/d inputs. these settings provide double the sample time at the same frequency. of course, settings intended for lower frequencies may also be used at higher frequencies in order to increase the a/d sampling time, but this method has the side effect of significantly increasing a/d conversion times. adint lsb msb bit symbol function adcon.7 e reserved for future use. should not be set to 1 by user programs. adcon.6 e reserved for future use. should not be set to 1 by user programs. adcon.5 e reserved for future use. should not be set to 1 by user programs. adcon.4 e reserved for future use. should not be set to 1 by user programs. adcon.3 adres selects 8-bit (0) or 10-bit (1) conversion mode. adcon.2 admod a/d mode select. 1 = continuous scan of selected inputs after a start of the a/d. 0 = single scan of selected inputs after a start of the a/d. adcon.1 adsst a/d start and status. setting this bit by software starts the a/d conversion of the selected a/d inputs. adsst remains set as long as the a/d is in operation. in continuous conversion mode, adsst will remain set unless the a/d is stopped by software. while adsst is set, new start commands are ignored. an a/d conversion is progress may be aborted by software clearing adsst. adcon.0 adint a/d conversion complete/interrupt flag. this flag is set when all selected a/d channels are converted in either the single scan or continuous scan modes. must be cleared by software. adsst admod adres e e e e adcon address:43eh bit addressable reset value: 00h su01229 figure 1. a/d control register (adcon)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 15 adcs0 lsb msb bit symbol function adcs.7 adcs7 a/d channel 7 select bit. adcs.6 adcs6 a/d channel 6 select bit. adcs.5 adcs5 a/d channel 5 select bit. adcs.4 adcs4 a/d channel 4 select bit. adcs.3 adcs3 a/d channel 3 select bit. adcs.2 adcs2 a/d channel 2 select bit. adcs.1 adcs1 a/d channel 1 select bit. adcs.0 adcs0 a/d channel 0 select bit. adcs1 adcs2 adcs3 adcs4 adcs5 adcs6 adcs7 adcs address:43fh bit addressable reset value: 00h su00939 figure 2. a/d channel select register (adcs) lsb msb bit symbol function adcfg.7 e reserved for future use. should not be set to 1 by user programs. adcfg.6 e reserved for future use. should not be set to 1 by user programs. adcfg.5 e reserved for future use. should not be set to 1 by user programs. adcfg.4 e reserved for future use. should not be set to 1 by user programs. adcfg.30 adcfg a/d timing configuration (see text and table). a/d timing configuration e e e e adcfg address:4b9h not bit addressable reset value: 00h su00940 figure 3. a/d timing configuration register (adcfg) table 2. a/d timing configuration adcfg 3 0 max. oscillator conversion time sampling time adcfg . 3 0 frequency (mhz) osc. clocks m sec at max. osc. pg (osc. clocks) 0h (0000) 6.66 72 10.81 4 1h (0001) 10 76 7.6 6 2h (0010) 11.11 80 7.2 8 3h (0011) 13.33 96 7.2 8 4h (0100) 16.66 100 6.0 10 5h (0101) 20 104 5.2 12 6h (0110) 1 20 116 5.8 24 7h (0111) 22.2 108 4.86 14 8h (1000) 23.3 124 5.32 14 9h (1001) 26.6 128 4.81 16 ah (1010) 30 132 4.4 18 bh (1011) 1 30 146 4.87 32 ch (1100) 136 4.25 20 dh (1101) 152 4.56 20 eh (1110) 172 4.7 22 fh (1111) 176 4.4 24 note: 1. these settings provide additional a/d input sampling time, in order to allow accurate readings with a higher external source impedance.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 16 table 3. a/d timing configuration for 10-bit mode adcfg 3 0 max. oscillator conversion time sampling time adcfg . 3 0 frequency (mhz) osc. clocks m sec at max. osc. pg (osc. clocks) 0h (0000) 6.66 88 13.21 4 1h (0001) 8 92 9.2 6 2h (0010) 8 96 8.64 8 3h (0011) 12 116 8.7 8 4h (0100) 12 120 7.2 10 5h (0101) 12 124 6.2 12 6h (0110) 12 136 6.8 24 7h (0111) 12 128 5.77 14 8h (1000) 13 148 6.35 14 9h (1001) 13 152 5.71 16 ah (1010) 13 156 5.2 18 bh (1011) 13 170 5.67 32 ch (1100) 13 160 5.0 20 dh (1101) 16 180 5.41 20 eh (1110) 20 204 5.57 22 fh (1111) 20 208 5.2 24 a/d inputs in order to obtain accurate measurements with the a/d converter, the source drive must be sufficient to adequately charge the sampling capacitor during the sampling time. figure 4 shows the equivalent resistance and capacitance related to the a/d inputs. a/d timing configurations indicated in table 1 allow for full a/d accuracy (according to the a/d specifications) assuming a source resistance of less than or equal to 20k w . larger source resistances may be accommodated by increasing the sampling time with a different a/d timing configuration. r s v analog input c s c c to comparator + ad n ad n+1 sm n+1 sm n rm n+1 rm n multiplexer r m (multiplexer resistance) = 3 k w maximum c s (pin capacitance) = 10 pf maximum c c (sampling capacitor) = 2 pf maximum r s (source resistance) = recommended less than 20k w for full specified accuracy. this allows time for the sampling capacitor (c c ) to fully charge while the multiplexer switch is closed. please note that sampling causes the analog input to present a varying load to the pin. su00948 figure 4. a/d input: equivalent circuit
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 17 a/d accuracy the xa-s3 a/d in 10 -bit mode is specified with 16 samples averaged in order to factor out on-chip noise. in an application where averaging 16 samples is not practical, the accuracy specifications may be de-rated according to the number of samples that are actually taken. the graph in figure 5 shows the relationship of additional a/d error to the number of samples that are averaged. for example, if a single a/d reading is used with no averaging, the a/d accuracy should be de-rated by 1.25 lsb. su01227 1.50 1.25 1.00 0.75 0.50 0.25 0.00 12345678910111213141516 number of samples additional error (lsb) figure 5. a/d accuracy by number of averaging samples (pertains to 10-bit mode only. note that 10-bit mode is only specified up to f c = 20 mhz.) cr0 lsb msb bit symbol function i2con.7 cr2 i 2 c rate control, with cr1 and cr0. see text and table. i2con.6 ena enable i 2 c port. when ena = 1, the i 2 c port is enabled. i2con.5 sta start flag. setting sta to 1 causes the i 2 c interface to attempt to gain mastership of the bus by generating a start condition. i2con.4 sto stop flag. setting sto to 1 causes the i 2 c interface to attempt to generate a stop condition. i2con.3 si serial interrupt. si is set by the i 2 c hardware when a new i 2 c state is entered, indicating that software needs to respond. si causes an i 2 c interrupt if enabled and of sufficient priority. i2con.2 aa assert acknowledge. setting aa to 1 causes the i 2 c hardware to automatically generate acknowledge pulses for various conditions (see text). i2con.1 cr1 i 2 c rate control, with cr2 and cr0. see text and table. i2con.0 cr0 i 2 c rate control, with cr2 and cr1. see text and table. cr1 aa si sto sta ena cr2 i2con address:42ch bit addressable reset value: 00h su00941 figure 6. i 2 c control register (i2con)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 18 i 2 c interface the i 2 c interface on the xa-s3 is identical to the standard byte-style i 2 c interface found on devices such as the 8xc552 except for the rate selection. the i 2 c interface conforms to the 100 khz i 2 c specification, but may be used at rates up to 400 khz (non-conforming). important: before the i 2 c interface may be used, the port pins p5.6 and 5.7, which correspond to the i 2 c functions scl and sda respectively, must be set to the open drain mode. the processor interfaces to the i 2 c logic via the following four special function registers: i2con (i 2 c control register), i2sta (i 2 c status register), i2dat (i 2 c data register), and i2adr (i 2 c slave address register). the i 2 c control logic interfaces to the external i 2 c bus via two port 5 pins: p5.6/scl (serial clock line) and p5.7/sda (serial data line). the control register, i2con this register is shown in figure 6. two bits are affected by the i 2 c hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ena = a0o. ena, the i 2 c enable bit ena = 0: when ena is a0o, the sda and scl outputs are not driven. sda and scl input signals are ignored, sio1 is in the anot addressedo slave state, and the sto bit in i2con is forced to a0o. no other bits are affected. p5.6 and p5.7 may be used as open drain i/o ports. ena = 1: when ena is a1o, sio1 is enabled. the p5.6 and p5.7 port latches must be set to logic 1. ena should not be used to temporarily release the i 2 c-bus since, when ena is reset, the i 2 c-bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text). in the following text, it is assumed the ena = a1o. sta, the start flag sta = 1: when the sta bit is set to enter a master mode, the i 2 c hardware checks the status of the i 2 c bus and generates a start condition if the bus is free. if the bus is not free, the i 2 c interface waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal serial clock generator. if sta is set while the i 2 c interface is already in a master mode and one or more bytes are transmitted or received, the hardware transmits a repeated start condition. sta may be set at any time. sta may also be set when the i 2 c interface is an addressed slave. sta = 0: when the sta bit is reset, no start condition or repeated start condition will be generated. sto, the stop flag sto = 1: when the sto bit is set while the i 2 c interface is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the hardware behaves as if a stop condition has been received and switches to the defined anot addressedo slave receiver mode. the sto flag is automatically cleared by hardware. if the sta and sto bits are both set, then a stop condition is transmitted to the i 2 c bus if the interface is in a master mode (in a slave mode, the hardware generates an internal stop condition which is not transmitted). the i 2 c interface then transmits a start condition. sto = 0: when the sto bit is reset, no stop condition will be generated. si, the serial interrupt flag si = 1: when the si flag is set, and the ea (interrupt system enable) and ei2 (i 2 c interrupt enable) bits are also set, an i 2 c interrupt is requested. si is set by hardware when one of 25 of the 26 possible i 2 c interface states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = 0: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. aa, the assert acknowledge flag aa = 1: if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: ? the aown slave addresso has been received. ? the general call address has been received while the general call bit (gc) in i2adr is set. ? a data byte has been received while the i 2 c interface is in the master receiver mode. ? a data byte has been received while the i 2 c interface is in the addressed slave receiver mode. aa = 0: if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on the scl line when: ? a data byte has been received while the i 2 c interface is in the master receiver mode. ? a data byte has been received while the i 2 c interface is in the addressed slave receiver mode. when the i 2 c interface is in the addressed slave transmitter mode, state c8h will be entered after the last serial data byte is transmitted. when si is cleared, the i 2 c interface leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when the i 2 c interface is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, the hardware can be temporarily released from the i 2 c bus while the bus status is monitored. while the hardware is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 19 cr0, cr1, and cr2, the clock rate bits these three bits determine the serial clock frequency when the i 2 c interface is in a master mode. an i 2 c rate of 100khz or lower is typical and can be derived from many oscillator frequencies. the various serial rates are shown in table 4. a variable bit rate may also be used if timer 1 is not required for any other purpose while the i 2 c hardware is in a master mode. the frequencies shown in table 4 are unimportant when the i 2 c hardware is in a slave mode. in the slave modes, the hardware will automatically synchronize with the incoming clock frequency. the i 2 c status register, i2sta i2sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when i2sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other i2sta values correspond to defined hardware interface states. when each of these states is entered, a serial interrupt is requested (si = a1o). note: a detailed i 2 c interface description and usage information, including example driver code, will be provided in a separate document. table 4. i 2 c rate control frequency select clock divisor example i 2 c rates at specific oscillator frequencies qy (cr2, cr1, cr0) clock divisor 8 mhz 12 mhz 16 mhz 20 mhz 24 mhz 30 mhz 0h (0000) 20 (400) 1 1h (0001) 40 (200) 1 (300) 1 (400) 1 2h (0010) 68 (116.65) 1 (176.46) 1 (235.29) 1 (294.12) 1 (352.94) 1 3h (0011) 88 90.91 (136.36) 1 (181.82) 1 (227.27) 1 (272.73) 1 (340.91) 1 4h (0100) 160 50 75 100 (125) 1 (150) 1 (187.5) 1 5h (0101) 272 29.41 44.12 58.82 73.53 88.24 (110.29) 1 6h (0110) 352 22.73 34.09 45.45 56.82 68.18 85.23 7h (0111) (timer 1) 2 (timer 1) 2 (timer 1) 2 (timer 1) 2 (timer 1) 2 (timer 1) 2 (timer 1) 2 notes: 1. the xa-s3 i 2 c interface does not conform to the 400khz i 2 c specification (which applies to rates greater than 100khz) in all details, but may be used with care where higher rates are required by the application. 2. the timer 1 overflow is used to clock the i 2 c interface. the resulting bit rate is 1/2 of the timer overflow rate.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 20 xa-s3 timer/counters the xa-s3 has three general purpose counter/timers, two of which may also be used as baud rate generators for either or both of the uarts. timer 0 and 1 these are identical to the standard xa-g3 timer 0 and 1. timer 2 this is identical to the standard xa-g3 timer 2. programmable counter array (pca) the programmable counter array available on the xa-s3 is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p4.1(cex0), module 1 to p4.2(cex1), etc. the basic pca configuration is shown in figure 7. the pca timer is a common time base for all five modules and can be programmed to run at: the tclk rate (osc/4, osc/16, or osc/64), the timer 0 overflow, or the input on the eci pin (p4.0). when the eci input is used, the falling edge clocks the pca counter. the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 10): cps1 cps0 pca timer count source 0 x tclk (osc/4, osc/16, or osc/64) 1 0 timer 0 overflow 1 1 eci (pca external clock input (max rate = osc/4) in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 8. in addition, each pca module may generate a separate interrupt. the watchdog timer function is implemented in module 4 (see figure 17). the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to figure 11). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the pca interrupt system shown in figure 9. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 12). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. figure 13 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p4.1/cex0 p4.2/cex1 p4.3/cex2 p4.4/cex3 p4.5/cex4 16 bits pca timer/counter time base for pca modules 16 bits su01303 figure 7. programmable counter array (pca)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 21 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (41ah) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (490h) cidl wdte cps1 cps0 ecf tclk (osc/4, osc/16, or osc/64) timer 0 overflow external input (p4.0/eci) decode 01 10 11 su01304 figure 8. pca timer/counter module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf ccapmn.0 eccfn to interrupt priority decoder ccon (41ah) iel.5 epc iel.7 ea su01305 figure 9. pca interrupt system
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 22 cmod address = 490h reset value = 00h cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 pca timer count source 0 x tclk (osc/4, osc/16, or osc/64) 1 0 timer 0 overflow 1 1 eci (pca external clock input (max rate = osc/4) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su01306 76543210 figure 10. cmod: pca counter mode register ccon address = 41ah reset value = 00h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. each of ccf4 through ccf0 generates its own interrupt, and has its own interrupt vector. note: * user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01307 76543210 figure 11. ccon: pca counter control register
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 23 ccapmn address ccapm0 491h ccapm1 492h ccapm2 493h ccapm3 494h ccapm4 495h reset value = 00h ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01308 76543210 figure 12. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 13. pca module modes (ccapmn register) pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. refer to figure 14. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 15). high speed output mode in this mode the cex output (on port 4) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 16). pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 17 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 24 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (41ah) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (491h495h) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su01309 figure 14. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (41ah) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (491h495h) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su01310 figure 15. pca compare mode
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 25 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (41ah) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (491h495h) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su01311 figure 16. pca high speed output mode cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (491h495h) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su01312 figure 17. pca pwm mode
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 26 ecomn cappn capnn matn togn pwmn eccfn ccapm4 (495h) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4h reset write to ccap4l 01 1 cmod (490h) cidl wdte cps1 cps0 ecf x su01313 module 4 figure 18. pca watchdog timer m(module 4 only) pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 18 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven low. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. figure 19 shows the code for initializing the watchdog timer. module 4 can be configured in either compare mode, and the wdte bit in cmod must also be set. the user's software then must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine in figure 19. this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 27 init_watchdog: mov ccapm4, #4ch ; module 4 in compare mode mov ccap4l, #0ffh ; write to low byte first mov ccap4h, #0ffh ; before pca timer counts up to ; ffff hex, these compare values ; must be changed or cmod, #40h ; set the wdte bit to enable the ; watchdog timer without changing ; the other bits in cmod ; ;******************************************************************** ; ; main program goes here, but call watchdog periodically. ; ;******************************************************************** ; watchdog: clr ea ; hold off interrupts mov ccap4l, #00 ; next compare value is within mov ccap4h, ch ; 255 counts of the current pca setb ea ; timer value ret figure 19. pca watchdog timer initialization code watchdog timer this is a standard xa-g3 watchdog timer. this watchdog timer always comes up running at reset. the watchdog acts the same on eprom, rom, and romless parts, as in the xa-g3. uarts standard xa-s3 uart0 and uart1 with double buffered transmit register. a flag has been added to snstat that is set if any of the status flags (brn, fen, or oen) is set for the corresponding uart channel. this allows polling for uart errors quickly at the interrupt service routine. baud rate sources may be timer 1 or timer 2. the xa-s3 includes 2 uart ports that are compatible with the enhanced uart used on the xa-g3. the uart has separate interrupt vectors for each uart's transmit and receive functions. the uart transmitter has been double buffered, allowing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. a break detect function has been added to the uart. this operates independently of the uart itself and provides a start-of-break status bit that the program may test. an overrun error flag allows detection of missed characters in the received data stream. the double buffered uart transmitter may require some software changes if code is used that was written for the original xa-g3 single buffered uart. each uart baud rate is determined by either a fixed division of the oscillator (in uart modes 0 and 2) or by the timer 1 or timer 2 overflow rate (in uart modes 1 and 3). timer 1 defaults to clock both uart0 and uart1. timer 2 can be programmed to clock either uart0 through t2con (via bits r0clk and t0clk) or uart1 through t2mod (via bits r1clk and t1clk). in this case, the uart not clocked by t2 could use t1 as the clock source. the serial port receive and transmit registers are both accessed at special function register snbuf. writing to snbuf loads the transmit register, and reading snbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial i/o expansion mode. serial data enters and exits through rxdn. txdn outputs the shift clock. 8 bits are transmitted/received (lsb first). (the baud rate is fixed at 1/16 the oscillator frequency.) mode 1: standard 8-bit uart mode. 10 bits are transmitted (through txdn) or received (through rxdn): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register sncon. the baud rate is variable. mode 2: fixed rate 9-bit uart mode. 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8_n in sncon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8_n. on receive, the 9th data bit goes into rb8_n in special function register sncon, while the stop bit is ignored. the baud rate is programmable to 1/32 of the oscillator frequency. mode 3: standard 9-bit uart mode. 11 bits are transmitted (through txdn) or received (through rxdn): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses snbuf as a destination register. reception is initiated in mode 0 by the condition ri_n = 0 and ren_n = 1. reception is initiated in the other modes by the incoming start bit if ren_n = 1.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 28 serial port control register the serial port control and status register is the special function register sncon, shown in figure 21. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8_n and rb8_n), and the serial port interrupt bits (ti_n and ri_n). ti flag in order to allow easy use of the double buffered uart transmitter feature, the ti_n flag is set by the uart hardware under two conditions. the first condition is the completion of any byte transmission. this occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. the second condition is when snbuf is written while the uart transmitter is idle. in this case, the ti_n flag is set in order to indicate that the second uart transmitter buffer is still available. typically, uart transmitters generate one interrupt per byte transmitted. in the case of the xa uart, one additional interrupt is generated as defined by the stated conditions for setting the ti_n flag. this additional interrupt does not occur if double buffering is bypassed as explained below. note that if a character oriented approach is used to transmit data through the uart, there could be a second interrupt for each character transmitted, depending on the timing of the writes to sbuf. for this reason, it is generally better to bypass double buffering when the uart transmitter is used in character oriented mode. this is also true if the uart is polled rather than interrupt driven, and when transmission is character oriented rather than message or string oriented. the interrupt occurs at the end of the last byte transmitted when the uart becomes idle. among other things, this allows a program to determine when a message has been transmitted completely. the interrupt service routine should handle this additional interrupt. the recommended method of using the double buffering in the application program is to have the interrupt service routine handle a single byte for each interrupt occurrence. in this manner the program essentially does not require any special considerations for double buffering. unless higher priority interrupts cause delays in the servicing of the uart transmitter interrupt, the double buffering will result in transmitted bytes being tightly packed with no intervening gaps. 9-bit mode please note that the ninth data bit (tb8) is not double buffered. care must be taken to insure that the tb8 bit contains the intended data at the point where it is transmitted. double buffering of the uart transmitter may be bypassed as a simple means of synchronizing tb8 to the rest of the data stream. bypassing double buffering the uart transmitter may be used as if it is single buffered. the recommended uart transmitter interrupt service routine (isr) technique to bypass double buffering first clears the ti_n flag upon entry into the isr, as in standard practice. this clears the interrupt that activated the isr. secondly, the ti_n flag is cleared immediately following each write to snbuf. this clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. if there is any possibility that a higher priority interrupt might become active between the write to snbuf and the clearing of the ti_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the ea bit in the iel register. clocking scheme/baud rate generation the xa uarts clock rates are determined by either a fixed division (modes 0 and 2) of the oscillator clock or by the timer 1 or timer 2 overflow rate (modes 1 and 3). the clock for the uarts in xa runs at 16x the baud rate. if the timers are used as the source for baud clock, since maximum speed of timers/baud clock is osc/4, the maximum baud rate is timer overflow divided by 16 i.e. osc/64. in mode 0, it is fixed at osc/16. in mode 2, however, the fixed rate is osc/32. 00 osc/4 pre-scaler for all timers t0 1 2 01 osc/16 f or a ll ti mers t0 , 1 , 2 controlled b y pt1 , pt0 10 osc/64 controlled by pt1, pt0 bits in scr 11 reserved baud rate for uart mode 0: baud_rate = osc/16 baud rate calculation for uart mode 1 and 3: baud_rate = timer_rate/16 timer_rate = osc/(n*(timer_range timer_reload_value)) where n = the tclk prescaler value: 4, 16, or 64. and timer_range = 256 for timer 1 in mode 2. 65536 for timer 1 in mode 0 and timer 2 in count up mode. the timer reload value may be calculated as follows: timer_reload_value = timer_range(osc/(baud_rate*n*16)) notes: 1.. the maximum baud rate for a uart in mode 1 or 3 is osc/64. 2.. the lowest possible baud rate (for a given oscillator frequency and n value) may be found by using a timer reload value of 0. 3.. the timer reload value may never be larger than the timer range. 4.. if a timer reload value calculation gives a negative or fractional result, the baud rate requested is not possible at the given oscillator frequency and n value. baud rate for uart mode 2: baud_rate = osc/32 using timer 2 to generate baud rates timer t2 is a 16-bit up/down counter in xa. as a baud rate generator, timer 2 is selected as a clock source for either/both uart0 and uart1 transmitters and/or receivers by setting tclkn and/or rclkn in t2con and t2mod. as the baud rate generator, t2 is incremented as osc/n where n = 4, 16 or 64 depending on tclk as programmed in the scr bits pt1, and pto. so, if t2 is the source of one uart, the other uart could be clocked by either t1 overflow or fixed clock, and the uarts could run independently with different baud rates. t2con bit5 bit4 0x418 rclk0 tclk0 t2mod bit5 bit4 0x419 rclk1 tclk1 prescaler select for timer clock (tclk) scr bit3 bit2 0x440 pt1 pt0
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 29 stintn bit symbol function snstat.3 fen framing error flag is set when the receiver fails to see a valid stop bit at the end of the frame. cleared by software. snstat.2 brn break detect flag is set if a character is received with all bits (including stop bit) being logic `0'. thus it gives a astart of break detecto on bit 8 for mode 1 and bit 9 for modes 2 and 3. the break detect feature operates independently of the uarts and provides the start of break detect status bit that a user program may poll. cleared by software. snstat.1 oen overrun error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while ri in sncon is still set. cleared by software. snstat.0 stintn this flag must be set to enable any of the above status flags to generate a receive interrupt (rin). the only way it can be cleared is by a software write to this register. su00607b oen brn fen e e e e snstat address: s0stat 421 s1stat 425 bit addressable reset value: 00h lsb msb figure 20. serial port extended status (snstat) register (see also figure 22 regarding framing error flag) uart interrupt scheme there are separate interrupt vectors for each uart's transmit and receive functions. table 5. interrupt vector locations for uarts vector address interrupt source arbitration a0h a3h uart 0 receiver 9 a4h a7h uart 0 transmitter 10 a8h abh uart 1 receiver 11 ach afh uart 1 transmitter 12 note: the transmit and receive vectors could contain the same isr address to work like a 8051 interrupt scheme error handling, status flags and break detect xa uarts have several error flags as described in figures 20 and 22. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit although this is better done with the framing error (fe) flag. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 23. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 30 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are teated as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. bit symbol function sncon.5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. sncon.4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. sncon.3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. the tb8 bit is not double buffered. see text for details. sncon.2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, if sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. sncon.1 ti transmit interrupt flag. set when another byte may be written to the uart transmitter. see text for details. must be cleared by software. sncon.0 ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the end of the stop bit time in the other modes (except see sm2). must be cleared by software. where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /16 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 1 1 3 9-bit uart variable su00597c ri ti rb8 tb8 ren sm2 sm1 sm0 sncon address: s0con 420 s1con 424 bit addressable reset value: 00h lsb msb figure 21. serial port control (sncon) register
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 31 d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit su00598 e e e e fen brn oen stintn snstat if 0, sets fe figure 22. uart framing error detection sm0_n sm1_n sm2_n ren_n tb8_n rb8_n ti_n ri_n sncon d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00613 figure 23. uart multiprocessor communication, automatic address recognition clocking / baud rate generation same as for the xa-g3. i/o port output configuration port output configurations are the same as for the xa-g3: open drain, quasi-bidirectional, push-pull, and off. external bus the external bus operates in the same manner as the xa-g3, but all 24 address lines are brought out to the outside world. this allows for a maximum of 16 mbytes of code memory and 16 mbytes of data memory. clock output the clkout pin allows easier external bus interfacing in some situations. this output reflects the x1 clock input to the xa, but is delayed to match the external bus outputs and strobes. the default is for clkout to be on at reset, but it may be turned off via the clkd bit that has been added to the bcr register. reset active low reset input, the same as the xa-g3. the associated rstout pin provides an external indication via an active low open drain output when an internal reset occurs. the rstout pin will be driven low when the rst pin is driven low, when a watchdog reset occurs or the reset instruction is executed. this signal may be used to inform other devices in a system that the xa-s3 has been reset. the latched values of ea and busw are not automatically updated when an internal reset occurs. rstout may be used to apply an external reset to the xa-s3 in order to update the previously latched ea and busw values. however, since rstout reflects all reset sources, it cannot simply be fed back into the rs t pin without other logic. the reset source identification register (rstsrc) indicates the cause of the most recent xa reset. the cause may have been an externally applied reset signal, execution of the reset instruction, or a watchdog reset. figure 24 shows the fields in the rstsrc register. power reduction modes the xa-s3 supports idle and power down modes of power reduction. the idle mode leaves some peripherals running in order to allow them to activate the processor when an interrupt is generated. the power down mode stops the oscillator in order to absolutely minimize power. the processor can be made to exit power down mode via a reset or one of the external interrupt inputs (int0 or int1). this will occur if the interrupt is enabled and its priority is higher than that defined by im3 through im0. in power down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram, register, and sfr contents at the point where power down mode was entered. v dd must be raised to within the operating range before power down mode is exited.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 32 lsb msb bit symbol function rstsrc.7 e reserved for future use. should not be set to 1 by user programs. rstsrc.6 e reserved for future use. should not be set to 1 by user programs. rstsrc.5 e reserved for future use. should not be set to 1 by user programs. rstsrc.4 e reserved for future use. should not be set to 1 by user programs. rstsrc.3 e reserved for future use. should not be set to 1 by user programs. rstsrc.2 r_wd indicates that the last reset was caused by a watchdog timer overflow. rstsrc.1 r_cmd indicates that the last reset was caused by execution of the reset instruction. rstsrc.0 r_ext indicates that the last reset was caused by the external rst input. e e e e rstsrc address:463h not bit addressable reset value: see below e r_wd r_cmd r_ext su00942 figure 24. reset source register (rstsrc) interrupts xa-s3 interrupt sources include the following: ? external interrupts 0 and 1 (2) ? timer 0, 1, and 2 interrupts (3) ? pca: 1 global and 5 channel interrupts (6) ? a/d interrupt (1) ? uart 0 transmitter and receiver interrupts (2) ? uart 1 transmitter and receiver interrupts (2) ? i 2 c interrupt (1) ? software interrupts (7) there are a total of 17 hardware interrupt sources, enable bits, priority bit sets, etc. the xa-s3 supports a total of 17 maskable event interrupt sources (for the various xa peripherals), seven software interrupts, 5 exception interrupts (plus reset), and 16 traps. the maskable event interrupts share a global interrupt disable bit (the ea bit in the iel register) and each also has a separate individual interrupt enable bit (in the iel or ieh registers). only three bits of the ipa register values are used on the xa-s3. each event interrupt can be set to occur at one of 8 priority levels via bits in the interrupt priority (ip) registers, ipa0 through ipa5. the value 0 in the ipa field gives the interrupt priority 0, in effect disabling the interrupt. a value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. the result is the same as if all four bits were used and the top bit set for all values except 0. details of the priority scheme may be found in the xa user guide . the complete interrupt vector list for the xa-s3, including all 4 interrupt types, is shown in the following tables. the tables include the address of the vector for each interrupt, the related priority register bits (if any), and the arbitration ranking for that interrupt source. the arbitration ranking determines the order in which interrupts are processed if more than one interrupt of the same priority occurs simultaneously. exception/traps precedence description vector address arbitration ranking reset (h/w, watchdog, s/w) 00000003 0 (high) breakpoint 00040007 1 trace 0008000b 1 stack overflow 000c000f 1 divide by 0 00100013 1 user reti 00140017 1 trap 015 (software) 0040007f 1
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 33 event interrupts description flag bit vector address enable bit interrupt priority arbitration ranking external interrupt 0 ie0 00800083 ex0 ipa0.20 (px0) 2 timer 0 interrupt tf0 00840087 et0 ipa0.64 (pt0) 3 external interrupt 1 ie1 0088008b ex1 ipa1.20 (px1) 4 timer 1 interrupt tf1 008c008f et1 ipa1.64 (pt1) 5 timer 2 interrupt tf2 (exf2) 00900093 et2 ipa2.20 (pt2) 6 pca interrupt ccf0ccf4, cf 00940097 epc ipa2.64 (ppc) 7 a/d interrupt adint 0098009b ead ipa3.20 (pad) 8 serial port 0 rx ri_0 00a000a3 eri0 ipa4.20 (pri0) 9 serial port 0 tx ti_0 00a400a7 eti0 ipa4.64 (pti0) 10 serial port 1 rx ri_1 00a800ab eri1 ipa5.20 (pri1) 11 serial port 1 tx ti_1 00ac00af eti1 ipa5.64 (pti1) 12 pca channel 0 ccf0 00c000c3 ec0 ipb0.20 (pc0) 17 pca channel 1 ccf1 00c400c7 ec1 ipb0.64 (pc1) 18 pca channel 2 ccf2 00c800cb ec2 ipb1.20 (pc2) 19 pca channel 3 ccf3 00cc00cf ec3 ipb1.64 (pc3) 20 pca channel 4 ccf4 00d000d3 ec4 ipb2.20 (pc4) 21 i 2 c interrupt si 00d400d7 ei2 ipb2.64 (pi2) 22 software interrupts description flag bit vector address enable bit interrupt priority software interrupt 1 swr1 01000103 swe1 (fixed at 1) software interrupt 2 swr2 01040107 swe2 (fixed at 2) software interrupt 3 swr3 0108010b swe3 (fixed at 3) software interrupt 4 swr4 010c010f swe4 (fixed at 4) software interrupt 5 swr5 01100113 swe5 (fixed at 5) software interrupt 6 swr6 01140117 swe6 (fixed at 6) software interrupt 7 swr7 0118011b swe7 (fixed at 7)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 34 absolute maximum ratings parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to v dd +0.5 v v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer, not device power consumption) 1.5 w dc electrical characteristics v dd = 2.7 v to 5.5 v, unless otherwise specified. t amb = 0 to +70 c for commercial, t amb = 40 c to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit i dd power supply current, operating 5.0 v, 30 mhz 80 ma i id power supply current, idle mode 5.0 v, 30 mhz 35 ma i pd power supply current, power down mode 5.0 v, 3.0 v 5 100 m a 5.0 v, 3.0 v, 40 to +85 c 150 m a v ram ram keep-alive voltage 1.5 v v il input low voltage 0.5 0.22 v dd v v ih input high voltage, except xtal1, rst v dd = 5.0 v 2.2 v v dd = 3.0 v 2.0 v v ih1 input high voltage to xtal1, rst for both 3.0 v and 5.0 v 0.7 v dd v v ol output low voltage, all ports, ale, psen 4 , clkout i ol = 3.2 ma, v dd = 5.0 v 0.5 v i ol = 1.0 ma, v dd = 3.0 v 0.4 v v oh1 output high voltage, all ports, ale, psen 2 , clkout i oh = 100 m a, v dd = 4.5 v 2.4 v i oh = 30 m a, v dd = 2.7 v 2.0 v v oh2 output high voltage, all ports ale, psen 3 , clkout i oh = 3.2 ma, v dd = 4.5 v 2.4 v i oh = 1.0 ma, v dd = 2.7 v 2.2 v c io input/output pin capacitance 1 15 pf i il logical 0 input current, all ports 7 v in = 0.45 v 50 m a i li input leakage current, all ports 6 v in = v il or v ih 10 m a i tl logical 1 to 0 transition current, all ports 5 at v dd = 5.5 v 650 m a at v dd = 2.7 v 250 m a notes: 1. maximum 15pf for ea /v pp . 2. ports in quasi-bidirectional mode with weak pullup (applies to ale, psen only during reset ). 3. ports in push-pull mode, both pullup and pulldown assumed to be the same strength. 4. in all output modes. 5. port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this current i s highest when v in is approximately 2 v. 6. measured with port in high impedance mode. 7. measured with port in quasi-bidirectional mode. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 35 8-bit mode a/d converter dc electrical characteristics t amb = 0 to +70 c for commercial, t amb = 40 to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min max unit av dd analog supply voltage 2.7 3.3 v ai dd analog supply current (operating) port 5 = 0 to av dd 2.5 ma ai id analog supply current (idle mode) 2.5 m a ai pd analog supply current (power-down mode) commercial temperature range 100 m a industrial temperature range 150 m a av in analog input voltage av ss 0.2 av dd +0.2 v r ref resistance between v ref+ and v ref 125 225 k w c ia analog input capacitance 15 pf dl e differential non-linearity 1, 2, 3 1 lsb il e integral non-linearity 1, 4 1 lsb os e offset error 1, 5 2.5 lsb g e gain error 1, 6 1 % a e absolute voltage error 1, 7 3 lsb m ctc channel-to-channel matching 1 lsb c t crosstalk between inputs of port 8 0 100 khz 60 db notes: 1. conditions: av ref = 0 v; av ref+ = 3.07 v. 2. the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. see figure 25. 3. the adc is monotonic, there are no missing codes. 4. the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 25. 5. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. see figure 25. 6. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset erro r), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve. see fig ure 25. 7. the absolute voltage error (a e ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 8. this should be considered when both analog and digital signals are input simultaneously to port 5. parameter is guaranteed by design.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 36 10-bit 10 mode a/d converter dc electrical characteristics t amb = 0 to +70 c for commercial, t amb = 40 to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min max unit av dd analog supply voltage 2.7 3.3 v ai dd analog supply current (operating) port 5 = 0 to av dd 2.5 ma ai id analog supply current (idle mode) 2.5 m a ai pd analog supply current (power-down mode) commercial temperature range 100 m a industrial temperature range 150 m a av in analog input voltage av ss 0.2 av dd +0.2 v r ref resistance between v ref+ and v ref 125 225 k w c ia analog input capacitance 15 pf dl e differential non-linearity 1, 2, 3 1 9 lsb il e integral non-linearity 1, 4 2.5 9 lsb os e offset error 1, 5 6 9 lsb g e gain error 1, 6 1 9 % a e absolute voltage error (with averaging) 1, 7 8 9 lsb m ctc channel-to-channel matching 1 lsb c t crosstalk between inputs of port 8 0 100 khz 60 db notes: 1. conditions: av ref = 0 v; av ref+ = 3.07 v. 2. the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. see figure 25. 3. the adc is monotonic, there are no missing codes. 4. the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 25. 5. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. see figure 25. 6. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset erro r), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve. see fig ure 25. 7. the absolute voltage error (a e ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 8. this should be considered when both analog and digital signals are input simultaneously to port 5. parameter is guaranteed by design. 9. 10-bit mode only. 10. 10-bit mode is only operational up to f c = 20 mhz.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 37 1 0 2 3 4 5 6 7 250 251 252 253 254 255 1 2 3 4 5 6 7 250 251 252 253 254 255 256 code out (2) (1) (5) (4) (3) 1 lsb (ideal) offset error os e offset error os e gain error g e av in (lsb ideal ) 1 lsb = av ref+ av ref 256 (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) center of a step of the actual transfer curve. su01010 full scale error fs e figure 25. adc conversion characteristic
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 38 ac electrical characteristics (5 v) v dd = 4.5 v to 5.5 v; t amb = 0 to +70 c for commercial, t amb = 40 c to +85 c for industrial. symbol figure parameter limits unit symbol figure parameter min max unit external clock f c 32 oscillator frequency 0 30 mhz t c 32 clock period and cpu timing cycle 1/f c ns t chcx 32 clock high-time (note 7) t c * 0.5 ns t clcx 32 clock low time (note 7) t c * 0.4 ns t clch 32 clock rise time (note 7) 5 ns t chcl 32 clock fall time (note 7) 5 ns address cycle t lhll 26, 28, 30 ale pulse width (programmable) (v1 * t c ) 6 ns t avll 26, 28, 30 address valid to ale de-asserted (set-up) (v1 * t c ) 12 ns t llax 26, 28, 30 address hold after ale de-asserted (t c /2) 10 ns code read cycle t plph 26 psen pulse width (v2 * t c ) 10 ns t llpl 26 ale de-asserted to psen asserted (t c /2) 7 ns t aviva 26 address valid to instruction valid, ale cycle (access time) (v3 * t c ) 36 ns t avivb 27 address valid to instruction valid, non-ale cycle (access time) (v4 * t c ) 29 ns t pliv 26 psen asserted to instruction valid (enable time) (v2 * t c ) 29 ns t phix 26 instruction hold after psen de-asserted 0 ns t phiz 26 bus 3-state after psen de-asserted t c 8 ns t ixua 26 hold time of unlatched part of address after instruction latched 0 ns data read cycle t rlrh 28 rd pulse width (v7 * t c ) 10 ns t llrl 28 ale de-asserted to rd asserted (t c /2) 7 ns t avdva 28 address valid to data input valid, ale cycle (access time) (v6 * t c ) 36 ns t avdvb 29 address valid to data input valid, non-ale cycle (access time) (v5 * t c ) 29 ns t rldv 28 rd low to valid data in (enable time) (v7 * t c ) 29 ns t rhdx 28 data hold time after rd deasserted 0 ns t rhdz 28 bus 3-state after rd de-asserted (disable time) t c 8 ns t dxua 28 hold time of unlatched part of address after data latched 0 ns data write cycle t wlwh 30 wr pulse width (v8 * t c ) 10 ns t llwl 30 ale falling edge to wr asserted (v12 * t c ) 10 ns t qvwx 30 data valid before wr asserted (data set-up time) (v13 * t c ) 22 ns t whqx 30 data hold time after wr de-asserted (note 6) (v11 * t c ) 5 ns t avwl 30 address valid to wr asserted (address set-up time) (note 5) (v9 * t c ) 22 ns t uawh 30 hold time of unlatched part of address after wr is de-asserted (v11 * t c ) 7 ns wait input t wth 31 wait stable after bus strobe (rd , wr , or psen ) asserted (v10 * t c ) 30 ns t wtl 31 wait hold after bus strobe (rd , wr , or psen ) asserted (v10 * t c ) 5 ns notes on page 41.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 39 ac electrical characteristics (5 v range) (continued) this set of parameters is referenced to the xa-s3 clock output. symbol figure parameter limits unit symbol figure parameter min max unit address cycle t chlh 26 clkout rising edge to ale rising edge 13 ns t clll 26 clkout falling edge to ale falling edge 9 ns t chav 26 clkout rising edge to address valid 18 ns t chax 26 clkout rising edge to address changing (hold time) 2 ns code read cycle t chpl 26 clkout rising edge to psen asserted 14 ns t chph 26 clkout rising edge to psen de-asserted 12 ns t ivch 26 instruction valid to clkout rising edge (setup time) 20 ns t chix 26 clkout rising edge to instruction changing (hold time) 0 ns t chiz 26 clkout rising edge to bus 3-state (code read) t c 8 ns data read cycle t chrl 28 clkout rising edge to rd asserted 12 ns t chrh 28 clkout rising edge to rd de-asserted 10 ns t dvch 28 data valid to clkout rising edge (setup time) 20 ns t chdx 28 clkout rising edge to data changing (hold time) 0 ns t chdz 28 clkout rising edge to bus 3-state (data read) t c 8 ns data write cycle t chwl 30 clkout falling edge to wr asserted 12 ns t chwh 30 clkout rising edge to wr de-asserted 10 ns t qvch 30 data valid to clkout rising edge (setup time) 4 ns t chqx 30 clkout rising edge to data changing (hold time) 0 ns wait input t chwth 31 wait valid prior to clkout rising edge 8 21 4 ns notes on page 41.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 40 ac electrical characteristics (3 v) v dd = 2.7 v to 4.5 v; t amb = 0 to +70 c for commercial, t amb = 40 c to +85 c for industrial. symbol figure parameter limits unit symbol figure parameter min max unit address cycle t lhll 26, 28, 30 ale pulse width (programmable) (v1 * t c ) 10 ns t avll 26, 28, 30 address valid to ale de-asserted (set-up) (v1 * t c ) 18 ns t llax 26, 28, 30 address hold after ale de-asserted (t c /2) 12 ns code read cycle t plph 26 psen pulse width (v2 * t c ) 12 ns t llpl 26 ale de-asserted to psen asserted (t c /2) 9 ns t aviva 26 address valid to instruction valid, ale cycle (access time) (v3 * t c ) 58 ns t avivb 27 address valid to instruction valid, non-ale cycle (access time) (v4 * t c ) 52 ns t pliv 26 psen asserted to instruction valid (enable time) (v2 * t c ) 52 ns t phix 26 instruction hold after psen de-asserted 0 ns t phiz 26 bus 3-state after psen de-asserted t c 8 ns t ixua 26 hold time of unlatched part of address after instruction latched 0 ns data read cycle t rlrh 28 rd pulse width (v7 * t c ) 12 ns t llrl 28 ale de-asserted to rd asserted (t c /2) 9 ns t avdva 28 address valid to data input valid, ale cycle (access time) (v6 * t c ) 58 ns t avdvb 29 address valid to data input valid, non-ale cycle (access time) (v5 * t c ) 52 ns t rldv 28 rd low to valid data in (enable time) (v7 * t c ) 52 ns t rhdx 28 data hold time after rd deasserted 0 ns t rhdz 28 bus 3-state after rd de-asserted (disable time) t c 8 ns t dxua 28 hold time of unlatched part of address after data latched 0 ns data write cycle t wlwh 30 wr pulse width (v8 * t c ) 12 ns t llwl 30 ale falling edge to wr asserted (v12 * t c ) 10 ns t qvwx 30 data valid before wr asserted (data set-up time) (v13 * t c ) 28 ns t whqx 30 data hold time after wr de-asserted (note 6) (v11 * t c ) 8 ns t avwl 30 address valid to wr asserted (address set-up time) (note 5) (v9 * t c ) 28 ns t uawh 30 hold time of unlatched part of address after wr is de-asserted (v11 * t c ) 10 ns wait input t wth 31 wait stable after bus strobe (rd , wr , or psen ) asserted (v10 * t c ) 40 ns t wtl 31 wait hold after bus strobe (rd , wr , or psen ) asserted (v10 * t c ) 5 ns notes on page 41.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 41 ac electrical characteristics (3 v range) (continued) this set of parameters is referenced to the xa-s3 clock output. symbol figure parameter limits unit symbol figure parameter min max unit address cycle t chlh 26 clkout rising edge to ale rising edge 15 ns t clll 26 clkout falling edge to ale falling edge 11 ns t chav 26 clkout rising edge to address valid 29 ns t chax 26 clkout rising edge to address changing (hold time) 2 ns code read cycle t chpl 26 clkout rising edge to psen asserted 16 ns t chph 26 clkout rising edge to psen de-asserted 15 ns t ivch 26 instruction valid to clkout rising edge (setup time) 30 ns t chix 26 clkout rising edge to instruction changing (hold time) 0 ns t chiz 26 clkout rising edge to bus 3-state (code read) t c 8 ns data read cycle t chrl 28 clkout rising edge to rd asserted 20 ns t chrh 28 clkout rising edge to rd de-asserted 16 ns t dvch 28 data valid to clkout rising edge (setup time) 28 ns t chdx 28 clkout rising edge to data changing (hold time) 0 ns t chdz 28 clkout rising edge to bus 3-state (data read) t c 8 ns data write cycle t chwl 30 clkout falling edge to wr asserted 19 ns t chwh 30 clkout rising edge to wr de-asserted 16 ns t qvch 30 data valid to clkout rising edge (setup time) 4 ns t chqx 30 clkout rising edge to data changing (hold time) 0 ns wait input t chwth 31 wait valid prior to clkout rising edge 8 30 4 ns notes: 1. load capacitance for all outputs = 50 pf. 2. variables v1 through v13 reflect programmable bus timing, which is programmed via the bus timing registers (btrh and btrl). r efer to the xa user guide for details of the bus timing settings. v1) this variable represents the programmed width of the ale pulse as determined by the alew bit in the btrl register. v1 = 0.5 if the alew bit = 0, and 1.5 if the alew bit = 1. v2) this variable represents the programmed width of the psen pulse as determined by the cr1 and cr0 bits or the cra1, cra0, and alew bits in the btrl register. for a bus cycle with no ale, v2 = 1 if cr1/0 = 00, 2 if cr1/0 = 01, 3 if cr1/0 = 10, and 4 if cr1/0 = 11. note that during burst mode code fetches, psen does not exhibit transitions at the boundaries of bus cycles. v2 still applies for the purpose of determining peripheral timing requirements. for a bus cycle with an ale, v2 = the total bus cycle duration (2 if cra1/0 = 00, 3 if cra1/0 = 01, 4 if cra1/0 = 10, and 5 if cra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5) = 2. example: if cra1/0 = 10 and alew = 1, the v2 = 4 (1.5 + 0.5) = 2. v3) this variable represents the programmed length of an entire code read cycle with ale. this time is determined by the cra1 and cra0 bits in the btrl register. v3 = the total bus cycle duration (2 if cra1/0 = 00, 3 if cra1/0 = 01, 4 if cra1/0 = 10, and 5 if cra1/0 = 11). v4) this variable represents the programmed length of an entire code read cycle with no ale. this time is determined by the cr1 and cr0 bits in the btrl register. v4 = 1 if cr1/0 = 00, 2 if cr1/0 = 01, 3 if cr1/0 = 10, and 4 if cr1/0 = 11. v5) this variable represents the programmed length of an entire data read cycle with no ale. this time is determined by the dr1 and dr0 bits in the btrh register. v5 = 1 if dr1/0 = 00, 2 if dr1/0 = 01, 3 if dr1/0 = 10, and 4 if dr1/0 = 11. v6) this variable represents the programmed length of an entire data read cycle with ale. the time is determined by the dra1 and dra0 bits in the btrh register. v6 = the total bus cycle duration (2 if dra1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and 5 if dra1/0 = 11).
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 42 v7) this variable represents the programmed width of the rd pulse as determined by the dr1 and dr0 bits or the dra1, dra0 in the btrh register, and the slew bit in the btrl register. note that during a 16-bit operation on an 8-bit external bus, rd remains low and does not exhibit a transition between the first and second byte bus cycles. v7 still applies for the purpose of determining peripheral timing requirements. the timing for the first byte is for a bus cycle with ale, the timing for the second byte is fo r a bus cycle with no ale. for a bus cycle with no ale, v7 = 1 if dr1/0 = 00, 2 if dr1/0 = 01, 3 if dr1/0 = 10, and 4 if dr1/0 = 11. for a bus cycle with an ale, v7 = the total bus cycle duration (2 if dra1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and 5 if dra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5). example: if dra1/0 = 00 and alew = 0, then v7 = 2 (0.5 +0.5) = 1. v8) this variable represents the programmed width of the wrl and/or wrh pulse as determined by the wm1 bit in the btrl register. v8 = 1 if wm1 = 0, and 2 if wm1 = 1. v9) this variable represents the programmed address setup time for a write as determined by the data write cycle duration (defin ed by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the value of v8. for a bus cycle with an ale, v9 = the total bus write cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8) minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example: if dwa1/0 = 10, wm0 = 1, and wm1 = 1, then v9 = 4 1 2 = 1. for a bus cycle with no ale, v9 = the total bus cycle duration (2 if dw1/0 = 00, 3 if dw1/0 = 01, 4 if dw1/0 = 10, and 5 if dw1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wmo = 0 and 1 if wm0 = 1). example: if dw1/0 = 11, wm0 = 1, and wm1 = 0, then v9 = 5 1 1 = 3. v10) this variable represents the length of a bus strobe for calculation of wait set-up and hold times. the strobe may be rd (for data read cycles), wrl and/or wrh (for data write cycles), or psen (for code read cycles), depending on the type of bus cycle being widened by wait. v10 = 2 for wait associated with a code read cycle using psen . v10 = v8 for a data write cycle using wrl and/or wrh . v10 = v7 1 for a data read cycle using rd . this means that a single clock data read cycle cannot be stretched using wait. if wait is used to vary the duration of data read cycles, the rd strobe width must be set to be at least two clocks in duration. also see note 4. v11) this variable represents the programmed write hold time as determined by the wm0 bit in the btrl register. v11 0 if the wm0 bit = 0, and 1 if the wm0 bit = 1. v12) this variable represents the programmed period between the end of the ale pulse and the beginning of the wrl and/or wrh pulse as determined by the data write cycle duration (defined by the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btr l register, and the values of v1 and v8. v12 = the total bus cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10 , and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1), minus the width of the ale pulse (v1). example: if swa1/0 = 11, wm0 = 1, wm1 = 0, and alew = 1, then v12 = 5 1 1 1.5 = 1.5. v13) this variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the values of v1 and v8. for a bus cycle with an ale, v13 = the total bus cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1), minus the number of clocks used by ale (v1 + 0.5). example: if dwa1/0 = 11, wm0 = 1, wm1 = 1, and alew = 0, then v13 = 5 1 2 1 = 1. for a bus cycle with no ale, v13 = the total bus cycle duration (2 if dw1/0 = 00, 3 if dw1/0 = 01, 4 if dw1/0 = 10, and 5 if dw1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example: if dw1/0 = 01, wm0 = 1, and wm1 = 0, then v13 = 3 1 1 = 1. 3. not all combinations of bus timing configuration values result in valid bus cycles. please refer to the xa user guide section on the external bus for details. 4. when code is being fetched for execution on the external bus, a burst mode fetch is used that dows not have psen edges in every fetch cycle. this would be a3a0 for an 8-bit bus, and a3a1 for a 16-bit bus. also, a 16-bit read operation conducted on an 8-bit wi de bus similarly does not include two separate rd strobes. so, a rising edge on the low order address line (a0) must be used to trigger a wait in the second half of such a cycle. 5. this parameter is provided for peripherals that have the data clocked in on the falling edge of the wr strobe. this is not usually the case and in most applications this parameter is not used. 6. please note that the xa-s3 requires that extended data bus hold time (wm0 = 1) to be used with external bus write cycles. 7. applies only to an external clock source, not when a crystal is connected to the xtal1 and xtal2 pins. 8. wait should not change between these times.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 43 ac waveforms t chlh t clll t lhll t chpl t chph t chav t chax t llpl t plph t ivch t avll t llax t pliv t chix t phiz t chiz t phix t aviva t ixua clkout ale psen multiplexed address and data unmultiplexed address a4a11 or a4a23 instr in* a0 or a1a3, a12a23 *instr in is either d0d7 or d0d15, depending on the bus width (8 or 16 bits). su00943a figure 26. external program memory read cycle (ale cycle) t avivb multiplexed address and data unmultiplexed address instr in* a0 or a1a3, a12a23 *instr in is either d0d7 or d0d15, depending on the bus width (8 or 16 bits). su00949 psen figure 27. external program memory read cycle (non-ale cycle)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 44 t lhll t chrl t chrh t llrl t rlrh t dvch t avll t llax t rldv t chdx t rhdz t chdz t rhdx t avdva t dxua clkout ale rd multiplexed address and data unmultiplexed address a4a11 or a4a23 data in* a0 or a1a3, a12a23 *data in is either d0d7 or d0d15, depending on the bus width (8 or 16 bits). su00944 figure 28. external data memory read cycle (ale cycle) t avdvb rd multiplexed address and data unmultiplexed address d0d7 a0a3, a12a23 su00950a figure 29. external data memory read cycle (non-ale cycle)
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 45 t chwl t chwh t llwl t wlwh t avll t llax t qvwx t chqx t whqx t avwl t uawh clkout ale wr multiplexed address and data unmultiplexed address a4a11 or a4a23 data out* a0 or a1a3, a12a23 *data out is either d0d7 or d0d15, depending on the bus width (8 or 16 bits). t qvch su00945 t chqz figure 30. external data memory write cycle xtal1 address bus wait su01068 t wtl ale bus strobe (wrl , wrh , rd , or psen ) t wth t crar (the dashed line shows the strobe without wait.) t chwth t chwtl figure 31. wait signal timing
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 46 v dd 0.5 0.45v 0.7v dd 0.2v dd 0.1 t chcl t c t clch t clcx t chcx su00842 figure 32. external clock drive v dd 0.5 0.45v 0.2v dd +0.9 0.2v dd 0.1 note: ac inputs during testing are driven at v dd 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at the 50% point of transitions. su00703a figure 33. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 34. float waveform v dd ea rst xtal1 xtal2 v ss v dd (nc) clock signal su00591b figure 35. i dd test condition, active mode all other pins are disconnected v dd ea rst xtal1 xtal2 v ss v dd (nc) clock signal su00590b v dd figure 36. i dd test condition, idle mode all other pins are disconnected
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 47 su01228 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 frequency (mhz) ma max. i dd (active) typical i dd (active) typical i dd (idle) max. i dd (idle) figure 37. i dd vs. frequency valid only within frequency specification of the device under test. v dd 0.5 0.45v 0.7v dd 0.2v dd 0.1 t chcl t cl t clch t clcx t chcx su00608a figure 38. clock signal waveform for i dd tests in active and idle modes t clch = t chcl = 5 ns v dd ea rst xtal1 xtal2 v ss (nc) su00585a v dd v dd figure 39. i dd test condition, power down mode all other pins are disconnected. v dd =2 v to 5.5 v
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 48 eprom characteristics the xa-s3 is programmed by using a modified improved quick-pulse programming ? algorithm. this algorithm is essentially the same as that used by 80c51 family eprom parts. however different pins are used for many programming functions. the xa-s3 contains three signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an xa-s3 manufactured by philips. security bits with none of the security bits programmed the code in the program memory can be verified. when only security bit 1 is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory. all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. (see table 6.) table 6. program security bits program lock bits sb1 sb2 sb3 protection description 1 u u u no program security features enabled. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, external execution is disabled. internal data ram is not accessible. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined. rom code submission when submitting rom code for the xa-s3, the following must be specified: 1. 32k byte user rom data 2. rom security bits. address content bit(s) comment 0000h to 7fffh data 7:0 user rom data 8020h sec 0 rom security bit 1 8020h sec 1 rom security bit 2 0 = enable security 1 = disable security 8020h sec 3 rom security bit 3 0 = enable security 1 = disable security ? trademark phrase of intel corporation.
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 49 plcc68: plastic leaded chip carrier; 68 leads; pedestal sot188-3
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 50 lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 51 notes
philips semiconductors preliminary specification xa-s3 xa 16-bit microcontroller 32 k/1 k otp/rom/romless, 8-channel 8-bit a/d, low voltage (2.7 v5.5 v), i 2 c, 2 uarts, 16 mb address range 2000 dec 01 52 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 12-00 document order number: 9397 750 07816

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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